In the fabrication of vertical, high performance bipolar transistors, it is generally desirable to provide very shallow intrinsic base regions. Such shallow intrinsic base regions, preferably in the sub-micron dimension range, permit the fabrication of high-frequency transistors: i.e. having speeds in the gigahertz range.
The formation of the intrinsic base region in the transistors described above is typically accomplished by diffusion from a gaseous or solid diffusion source, or by ion implantation (I/I). Diffusion tends to be difficult to control, and may result in undesirably thick base regions. Ion implantation, while more controllable than diffusion, also has inherent limitations, for example implant damage and channeling effects. Particularly with respect to ion implantation of boron atoms, the thickness of the implanted region is limited by secondary channeling effects. Further, both diffusion and ion implantation are particularly difficult to utilize with transistors having shallow, heterojunction base regions: i.e. silicon-germanium (SiGe) base regions.
In U.S. Pat. No. 4,504,332 to Shinada, a layer of silicon is epitaxially deposited over a partially insulated substrate, so as to be single crystal in structure where it contacts the substrate, and polycrystalline in structure where it contacts the insulator. The base region is deposited into the single crystal region of the layer by ion implantation, while the emitter region is deposited into the base region by outdiffusion from a solid doping source. There is thus completed a bipolar transistor. Shinada, however, shows a relatively thick deposited layer, with relatively thick and uncontrolled base and emitter regions. The teachings of Shinada could not readily be used to provide narrow base, high-performance bipolar transistors of the type typically in use today.
A process of low temperature, ultra-high vacuum, chemical vapor deposition is known in the art for forming thin, discretely doped layers of epitaxial silicon (or heterojunction material such as SiGe). See Meyerson, B., "Low Temperature Silicon Epitaxy by Ultra-high Vacuum/Chemical Vapor Deposition," Appl. Phys. Lett. 48(12), 24 March 1986, pgs. 797-799. This process, also known as low temperature epitaxy (LTE), has been used to form various device regions, including, in certain limited configurations, the base regions of transistors. The process is advantageous for these purposes in that it provides relatively defect-free, thin layers. This same thinness of the layers, however, makes it difficult to provide high-yield, defect-free devices and structures. Such thin layers are prone to the propogation of dislocation defects, this propogation caused by high temperature processes, such as annealing. Heterogeneous layers of SiGe are especially prone to such defects, particularly if the Ge concentration is greater than 10%.
"Buried emitter," also known as "collector-up," bipolar transistor structures are known in the art wherein an emitter region is formed in or buried in a semiconductor substrate, while a collector region is formed at or over the top of the substrate. Among other recognized advantages, such devices tend to be highly immune to alpha particle and cosmic-ray induced disturbances.
U.S. Pat. No. 4,956,689 to Yuan et al. shows a collector-up, gallium arsenide, bipolar transistor wherein the emitter-base junction is defined within a bottom of a trench etched in a layered gallium arsenide structure. The base region is formed by implanting dopant into undoped portions of the layered gallium arsenide structure within the trench. The collector region is formed by growth of an epitaxial layer over the base region.
The structure of Yuan et al. is prone to the disadvantages of high collector-base capacitance, high extrinsic base resistance, and ion implantation defects within the base region.
A class of buried emitter devices well known in the art is that referred to as integrated injection logic (I2L). In I2L, a vertical NPN transistor is integrated with a lateral PNP transistor, such that the two transistors share common semiconductor regions. The vertical NPN is typically configured with a buried emitter. See, for example, U.S. Pat. No. 4,210,925 to Morcom et al.
With the art of semiconductor devices tending towards increased miniaturization and device density, it is highly desirable to provide compact, state-of-the-art transistor structures, and particularly those utilizing narrow base regions realizable by a repeatable, reliable process. It is further desirable if such structures and processes can accommodate buried emitter transistors, and the known advantages inherent therein.